Analog to Digital Converter (ADC):
-----------------------------------------------
used to convert Analog signals to digital value.
Types of ADC:
==============
1- Ramp Counter ADC:-
--------------------------------
The idea behind this type of ADCs is that:
The Counter is Enabled by Zero (Active LOW). When the desired signal (Vin) > DAC output(which is a voltage too) the comparator output is Zero (0) Enabling the timer to continue to count. When the desired signal is equal to the DAC output, the comparator output is 1 disabling the counter from counting. The last value in the Counter is the digital representation of the analog signal.
-------------------------------------------------------------------------------------------------------------------
The step size is the voltage difference between one digital level (i.e. 0001) and the next one (i.e. 0010 or 0000).
step size = Vref. / (2^Resolution)
(2^Resolution) referred to Number of levels (Quantization).
Ex:
Vref.=5Volt. in 2 bit ADC so Step = 5/2^2=5/4=1.25 Volt
so ADC will have 4 different digital values(4 Levels) corresponding to analog signals of (0 , 1.25 , 2.5 , 3.75 , 5 Volt)
*Rem:
DAC is unable to produce its Vref. (Max. Voltage) as it is saturated at (Vmax-Step) which means the last level (digital representation) will be the same for (Vmax-Step) to (Vmax).
Ex: ADC , Vref = 5V , Resolution:8 Bit , Digital Value = 1111 1111
Analog Value = 255 * (5/256) = 4.9804 Volt => ( 5 - 0.0195 ) => (Vmax.-Step)
*Note:
---------
-Increasing ADC resolution means increasing ADC accuracy.
-Increasing Vref. means increasing measurement range.
Vref. Calculations:
------------------------
Vref is determined according to:
1- Max. Volt. will be measured from a sensor/transducer should be less than or equal Vref. of an ADC.
2- Generated Error in measurement. as when a sensor generates a max. volt of 2 is used with 2 bit ADC with Vref. =5 this will make a step of ( 5/4)=1.25 volt. which means that the ADC will only sense 0 and 1.25 Volt of the sensor ! which means a high error in reading the sensor's reading.But, if the same ADC is used with Vref. =2Volt that makes the Step=2/4=0.5 volt so the ADC will sense the 4 levels for the sensor's reading (0,0.5,1.5,2)!
-----------------------------------------------------------------------------------------------------------------
Problems with Ramp. Counter ADC:-
----------------------------------------------------
1- Increasing counter clock will increase the error in reading the digital representation as the counter will continue to count above the desired digital representation as a result of the delay between moving the digital representation from counter to DAC to convert it to an analog signal to be compared with the desired signal.
2- Increasing counter clock will decrease conversion time and as a result conversion time is not constant.
======================================================================
2- Successive Approximation ADC (SAR ADC) :-
-------------------------------------------------------------
It has 3 main Components:
---------------------------------
1- SAR "Successive Approximation Register"
2- Comparator
3- Control Unit
The main idea depends on :
if Analog Volt. (DAC Output) > Vin so the corresponding bit is cleared otherwise it's kept as 1.
Steps: (Assuming: 8 Bit SAR ADC , Step Size=10 mV, Vin=1Volt.):-
------------------------------------------------------------------------------------
1- Starts with binary 1000 0000 (128 in decimal)=> Analog Volt = 128 * 10 mV = 1.28 Volt. > Vin
so bit 7 is cleared(dropped).
2- 0100 0000 (64 in decimal) => Analog Volt = 64 * 10 mV=640 mV < Vin so bit 6 kept as 1.
3- 0110 0000 (96 in decimal) => Analog Volt=96*10 mV=960 mV < Vin so bit 5 kept as 1.
4- 0111 0000 (112 in decimal) => Analog Volt= 112*10mV=1.12 V > Vin so bit 4 is cleared.
5- 0110 1000 (108 in decimal) => Analog Volt=108*10mV=1.08V > Vin so it 3 is cleared.
6- 0110 0100 (100 in decimal) => Analog Volt=100*10mV=1V = Vin so bit 2 is kept as 1.
7- 0110 0110 (102 in decimal) => Analog Vol=102*10mV=1.02mV > Vin so bit 1 is cleared.
8- 0110 0101 (101 in decimal) => Analog Vol=101*10mV=1.01 mV > Vin so it 1 is cleared.
9- 0110 0100 is the final representation of 1Volt. input.
Result After 8 Clock Cycles:
-------------------------------------
so 1 Volt = > 0110 0100
--------------------------------------
Advantages:
------------------
Conversion time is constant.
Comparison between Ramp. Counter ADC and SAR ADC:
---------------------------------------------------------------------------
3- Flash ADC
----------------------
4- Integrator ADC
-------------------------
ADC peripheral in ATmega32:-
------------------------------------------
0.5 LSB Integral Non-linearity:
-Integral Non-linearity :
the maximum deviation of the ADC transfer function from the best fit line.
Steps size is not equal as a result of using resistors in DAC internally in the ADC this accumulated error in reading called Integral Non-linear error and equals 0.5 Least significant bit (half step) (Integral Non-linearity is expressed in LSBs) because the difference between two levels will happen in the LSB ex: 0000(level 0 on 0V) -> 0001(Level 1 on full step +/- half step) (the change happened is the LSB).
+/-2 LSB Absolute Accuracy:
as a result of 0.5 LSB Integral Non-linearity, the absolute error in conversion may happen in the least two significant bits.
13uSec to 260uSec Conversion time:
as the SAR ADC based on SAR timer which works with a clock with a prescalar so this prescalar varies the conversion time from 13 Microsecond (Fast conversion) to 260 Microsecond (Slow Conversion).
Up to 15 kSPS at Max. Resolution:
At Max. Resolution the ADC(10 bits) can convert 15 Kilo Sample per second (kSPS).
which means Max. Frequency of a signal that can be converted is 7.5 kHz according to Nyquist theory " Sampling frequency should be equal or greater than 2*signal Frequency". That ADC can convert human voices which have max. frequency of 4 kHz.
8 Multiplexed Single-Ended Input Channel:
means that there's only one ADC chip but the input of that ADC is branched to 8 channels on 8 pins with a multiplexer that determines which one will be the ADC input (only one at a time).
7 Differential Input Channels:
means we can use two pins to convert the difference between them to a digital value.
use case: measuring negative voltage, we can use two pins to do so.
2 Differential Input Channels with Optional Gain of 10x and 200x:
means we can use two pins to convert the difference between them then multiply it with a gain of 10 or 200 then convert that last value. we can use this feature to amplify a sensor's output.
Optional Left Adjustment for ADC Result Readout:
as the ADC is 10-bit resolution, it occupies two 8 bit registers but we can use only 10 bits starting from the right (right adjusted) or 10 bits starting from the left (left adjusted).
0-Vcc ADC Input Voltage Range
Selectable 2.56 V ADC Reference Voltage
Free Running or Single Conversion Mode:
Free Running means you need only to enable the ADC and conversion will automatically happen and continues and a programmer should read conversion result continuously if needed.
Single Conversion Mode means it only converts one time only then stops.
ADC start Conversion by Auto Triggering on Interrupt Sources:
means ADC will start conversion when a specific interrupt occurs.
Interrupt on ADC Conversion Complete:
means ADC will generate an interrupt when conversion is completed.
Sleep Mode Noise Canceler:
means that the ADC can be used to wake the micocontroller from the sleep mode with a specific value on ADC pin and the ADC can differentiate between noise and the analog signal using this mode.
ADC Driver (ATmega32):-
=====================
Concepts:
--------------
* Polling -Blocking cod: lines of a code block the remaining code from execution until those lines are executed first. i.e: while (flag==1);
*Polling-Non Blocking: polling on a flag during the code but not blocking the remaining code. i.e:
if (flag==1) { /*Code1*/} else {/*Code2*/}
* Non-Blocking (using Interrupts)
* Interrupt Saturation: entering nested interrupts for a long time preventing executing the main code.
===================================================================
APIs:
--------
1- ADC_init(void): initializes the following according configuration :
Vref. , ADC Presecaler , ADC Adjustment , Enable ADC
2- getADCBlocking(u8 ADC_Channel , u8 * Copy_pu8ADCReading ) :
A- Select ADC Channel
B- Start Conversion
C- Wait until conversion finished
D- Read ADC
3- getADCNonBlocking(u8 ADC_Channel , u8 * Copy_pu8ADCReading ):
A- Select ADC Channel
B- Start Conversion
C- Read ADC from ADC ISR
4- ADC_Refresh(void):
A- Start Conversion of a specific channel / first channel
B- when the first conversion finished, conversion value should be stored in ADC ISR execution and the second channel conversion should start and repeat this for a giver channels number.
5- ADCSetCallBack(void (*vPtr)(void)):
executes a specific function when conversion finishes.
==================================================================
Configurations :-
-----------------------
#define
- prescalar
-resolution=> 8 or 10 bits
-Vref => internal , internal/2 , external
- Number of active channels
- start channel
- end channel
- Adjustment (Right Adjusted or Left Adjusted)
===================================================================
-----------------------------------------------
used to convert Analog signals to digital value.
Types of ADC:
==============
1- Ramp Counter ADC:-
--------------------------------
The Counter is Enabled by Zero (Active LOW). When the desired signal (Vin) > DAC output(which is a voltage too) the comparator output is Zero (0) Enabling the timer to continue to count. When the desired signal is equal to the DAC output, the comparator output is 1 disabling the counter from counting. The last value in the Counter is the digital representation of the analog signal.
-------------------------------------------------------------------------------------------------------------------
The step size is the voltage difference between one digital level (i.e. 0001) and the next one (i.e. 0010 or 0000).
step size = Vref. / (2^Resolution)
(2^Resolution) referred to Number of levels (Quantization).
Ex:
Vref.=5Volt. in 2 bit ADC so Step = 5/2^2=5/4=1.25 Volt
so ADC will have 4 different digital values(4 Levels) corresponding to analog signals of (0 , 1.25 , 2.5 , 3.75 , 5 Volt)
*Rem:
DAC is unable to produce its Vref. (Max. Voltage) as it is saturated at (Vmax-Step) which means the last level (digital representation) will be the same for (Vmax-Step) to (Vmax).
Analog Value = Digital Representation * Step
Ex: ADC , Vref = 5V , Resolution:8 Bit , Digital Value = 1111 1111
Analog Value = 255 * (5/256) = 4.9804 Volt => ( 5 - 0.0195 ) => (Vmax.-Step)
*Note:
---------
-Increasing ADC resolution means increasing ADC accuracy.
-Increasing Vref. means increasing measurement range.
Vref. Calculations:
------------------------
Vref is determined according to:
1- Max. Volt. will be measured from a sensor/transducer should be less than or equal Vref. of an ADC.
2- Generated Error in measurement. as when a sensor generates a max. volt of 2 is used with 2 bit ADC with Vref. =5 this will make a step of ( 5/4)=1.25 volt. which means that the ADC will only sense 0 and 1.25 Volt of the sensor ! which means a high error in reading the sensor's reading.But, if the same ADC is used with Vref. =2Volt that makes the Step=2/4=0.5 volt so the ADC will sense the 4 levels for the sensor's reading (0,0.5,1.5,2)!
-----------------------------------------------------------------------------------------------------------------
Problems with Ramp. Counter ADC:-
----------------------------------------------------
1- Increasing counter clock will increase the error in reading the digital representation as the counter will continue to count above the desired digital representation as a result of the delay between moving the digital representation from counter to DAC to convert it to an analog signal to be compared with the desired signal.
2- Increasing counter clock will decrease conversion time and as a result conversion time is not constant.
======================================================================
2- Successive Approximation ADC (SAR ADC) :-
-------------------------------------------------------------
It has 3 main Components:
---------------------------------
1- SAR "Successive Approximation Register"
2- Comparator
3- Control Unit
The main idea depends on :
if Analog Volt. (DAC Output) > Vin so the corresponding bit is cleared otherwise it's kept as 1.
Steps: (Assuming: 8 Bit SAR ADC , Step Size=10 mV, Vin=1Volt.):-
------------------------------------------------------------------------------------
1- Starts with binary 1000 0000 (128 in decimal)=> Analog Volt = 128 * 10 mV = 1.28 Volt. > Vin
so bit 7 is cleared(dropped).
2- 0100 0000 (64 in decimal) => Analog Volt = 64 * 10 mV=640 mV < Vin so bit 6 kept as 1.
3- 0110 0000 (96 in decimal) => Analog Volt=96*10 mV=960 mV < Vin so bit 5 kept as 1.
4- 0111 0000 (112 in decimal) => Analog Volt= 112*10mV=1.12 V > Vin so bit 4 is cleared.
5- 0110 1000 (108 in decimal) => Analog Volt=108*10mV=1.08V > Vin so it 3 is cleared.
6- 0110 0100 (100 in decimal) => Analog Volt=100*10mV=1V = Vin so bit 2 is kept as 1.
7- 0110 0110 (102 in decimal) => Analog Vol=102*10mV=1.02mV > Vin so bit 1 is cleared.
8- 0110 0101 (101 in decimal) => Analog Vol=101*10mV=1.01 mV > Vin so it 1 is cleared.
9- 0110 0100 is the final representation of 1Volt. input.
Result After 8 Clock Cycles:
-------------------------------------
so 1 Volt = > 0110 0100
--------------------------------------
Advantages:
------------------
Conversion time is constant.
Comparison between Ramp. Counter ADC and SAR ADC:
---------------------------------------------------------------------------
3- Flash ADC
----------------------
4- Integrator ADC
-------------------------
ADC peripheral in ATmega32:-
------------------------------------------
0.5 LSB Integral Non-linearity:
-Integral Non-linearity :
the maximum deviation of the ADC transfer function from the best fit line.
Steps size is not equal as a result of using resistors in DAC internally in the ADC this accumulated error in reading called Integral Non-linear error and equals 0.5 Least significant bit (half step) (Integral Non-linearity is expressed in LSBs) because the difference between two levels will happen in the LSB ex: 0000(level 0 on 0V) -> 0001(Level 1 on full step +/- half step) (the change happened is the LSB).
+/-2 LSB Absolute Accuracy:
as a result of 0.5 LSB Integral Non-linearity, the absolute error in conversion may happen in the least two significant bits.
13uSec to 260uSec Conversion time:
as the SAR ADC based on SAR timer which works with a clock with a prescalar so this prescalar varies the conversion time from 13 Microsecond (Fast conversion) to 260 Microsecond (Slow Conversion).
Up to 15 kSPS at Max. Resolution:
At Max. Resolution the ADC(10 bits) can convert 15 Kilo Sample per second (kSPS).
which means Max. Frequency of a signal that can be converted is 7.5 kHz according to Nyquist theory " Sampling frequency should be equal or greater than 2*signal Frequency". That ADC can convert human voices which have max. frequency of 4 kHz.
8 Multiplexed Single-Ended Input Channel:
means that there's only one ADC chip but the input of that ADC is branched to 8 channels on 8 pins with a multiplexer that determines which one will be the ADC input (only one at a time).
7 Differential Input Channels:
means we can use two pins to convert the difference between them to a digital value.
use case: measuring negative voltage, we can use two pins to do so.
2 Differential Input Channels with Optional Gain of 10x and 200x:
means we can use two pins to convert the difference between them then multiply it with a gain of 10 or 200 then convert that last value. we can use this feature to amplify a sensor's output.
Optional Left Adjustment for ADC Result Readout:
as the ADC is 10-bit resolution, it occupies two 8 bit registers but we can use only 10 bits starting from the right (right adjusted) or 10 bits starting from the left (left adjusted).
0-Vcc ADC Input Voltage Range
Selectable 2.56 V ADC Reference Voltage
Free Running or Single Conversion Mode:
Free Running means you need only to enable the ADC and conversion will automatically happen and continues and a programmer should read conversion result continuously if needed.
Single Conversion Mode means it only converts one time only then stops.
ADC start Conversion by Auto Triggering on Interrupt Sources:
means ADC will start conversion when a specific interrupt occurs.
Interrupt on ADC Conversion Complete:
means ADC will generate an interrupt when conversion is completed.
Sleep Mode Noise Canceler:
means that the ADC can be used to wake the micocontroller from the sleep mode with a specific value on ADC pin and the ADC can differentiate between noise and the analog signal using this mode.
ADC Driver (ATmega32):-
=====================
Concepts:
--------------
* Polling -Blocking cod: lines of a code block the remaining code from execution until those lines are executed first. i.e: while (flag==1);
*Polling-Non Blocking: polling on a flag during the code but not blocking the remaining code. i.e:
if (flag==1) { /*Code1*/} else {/*Code2*/}
* Non-Blocking (using Interrupts)
* Interrupt Saturation: entering nested interrupts for a long time preventing executing the main code.
===================================================================
APIs:
--------
1- ADC_init(void): initializes the following according configuration :
Vref. , ADC Presecaler , ADC Adjustment , Enable ADC
2- getADCBlocking(u8 ADC_Channel , u8 * Copy_pu8ADCReading ) :
A- Select ADC Channel
B- Start Conversion
C- Wait until conversion finished
D- Read ADC
3- getADCNonBlocking(u8 ADC_Channel , u8 * Copy_pu8ADCReading ):
A- Select ADC Channel
B- Start Conversion
C- Read ADC from ADC ISR
4- ADC_Refresh(void):
A- Start Conversion of a specific channel / first channel
B- when the first conversion finished, conversion value should be stored in ADC ISR execution and the second channel conversion should start and repeat this for a giver channels number.
5- ADCSetCallBack(void (*vPtr)(void)):
executes a specific function when conversion finishes.
==================================================================
Configurations :-
-----------------------
#define
- prescalar
-resolution=> 8 or 10 bits
-Vref => internal , internal/2 , external
- Number of active channels
- start channel
- end channel
- Adjustment (Right Adjusted or Left Adjusted)
===================================================================
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